1. Field of the Invention
This invention relates to a semiconductor memory device, and in particular to an electrically erasable and writable non-volatile semiconductor memory device such as a flash memory or an EEPROM.
2. Description of Related Art
Since in the flash memory, memory data can be changed by means of an external panel or a remotely controlled operation while it is incorporated in a system, and also the capacity thereof can be easily enlarged, it has been increasingly utilized in various fields.
A data writing operation of flash memory will be explained with reference to FIG. 2 where the constitution of a memory cell of ordinary flash memory and a writing method thereof are shown. As shown in FIG. 2, a memory cell M of flash memory is constituted of a single MOS transistor comprising a control gate GC and a floating gate GF. When a data is written into the memory cell M, a voltage is impressed on each of the control gate GC and a drain D to generate a channel current, which current in turn causes the generation of hot carriers due to a collision ionization. When electrons from the hot carriers enter the floating gate GF and are trapped by the oxide film of the floating gate GF, the writing of data is effected. The threshold voltage of the memory cell after the writing of data will become higher than that of the memory cell in which data has not been written due to negative charges accumulated in the oxide film of the floating gate GF.
Referring to FIG. 1 where a conventional semiconductor memory device is indicated by blocks, the conventional semiconductor memory device comprises a data writing unit 100 for writing data into a flash memory cell, a CPU 2, and a supply voltage-detecting circuit 3 which outputs a voltage drop signal POC when a supply voltage VDD falls below a reference voltage. The data writing unit 100 includes an X-decoder 11 for decoding an X address of a memory cell supplied from the CPU 2, a Y-decoder 12 for decoding a Y address of a memory cell supplied from the CPU 2, a memory cell array 114 in which flash memory cells are arranged in rows and columns, a read/write circuit 116 for effecting reading/writing of data of the memory cell array 114 in response to a Y-decode signal, and a system power source 117 for supplying a voltage for the writing.
Next, the operation of the conventional semiconductor memory device will be explained with reference to FIG. 1.
The CPU 2 feeds a write signal WRT to the Y-decoder 12 and the read/write circuit 116. And the CPU 2 feeds an address signal ADDRESS to the X-decoder 11 and the Y-decoder 12. The Y-decoder 12 feeds a Y-decode signal to the read/write circuit 116, where a bit line of the memory cell array 114 corresponding to the Y-decode signal is selected. The system power source 117 applies a writing voltage VPW to the bit line thus selected via the read/write circuit 116. Meanwhile, the system power source 117 applies a high voltage VPP via the X-decoder 11 to a word line of the memory cell array 114 which has been selected by an X-decode signal supplied from the X-decoder 11. As a result, different high voltages VPP and VPW are applied to a gate GC and drain D, respectively, of a memory cell selected in the memory cell array 114 (hereinafter referred to as a selected memory cell) thereby performing the writing of data by a hot carrier effect as mentioned above.
Since the writing of data is performed by utilizing a physical phenomenon of a MOS transistor as explained above, any drop of voltage impressed on each terminal of a selected memory cell in the memory cell array 114 gives a bad influence directly to the writing of data. As a countermeasure for this problem, a supply voltage-detecting circuit 3 for detecting a drop of supply voltage is separately provided. The circuit 3 sends a voltage drop-detecting signal POC "1" to the CPU 2 when supply voltage VDD falls below a reference value. The CPU 2 in turn prevents any access to the memory cell array 114 in response to the signal POC "1". However, since the supply voltage-detecting circuit 3 is located remote from the memory cell array 114, the supply voltage-detecting circuit 3 does not output a voltage drop-detecting signal POC in the case where an that impressing voltage, such as VPW and VPP falls below a reference value, when data is written. The voltage drop-detecting signal POC is not output due to possible wiring current and parasitic resistance of wiring, or due to inner resistance within a power source, relating to the memory cell array 114. As a result, the CPU 2 fails to forbid the writing in the memory cell array 114, so that writing is performed. Generally, an allowance in the range of voltage drop of impressing voltage for the writing of flash memory is very narrow, i.e., the allowance in the range of voltage drop according to the specification of actual products is specified as being -0.3V; therefore, if the range of voltage drop of the impressing voltage at the writing exceeds the allowance, writing errors of data will occur.
Since the writing of data in the aforementioned conventional semiconductor memory device is performed by utilizing a hot carrier effect of a MOS transistor, the device is provided with a supply voltage-detecting circuit for detecting any drop in supply voltage that may cause inferior writing. However, since the supply voltage-detecting circuit is located remote from the memory cell array of the device, voltage drop at (i.e., during) the writing of data due to parasitic resistance of wiring or the like cannot be detected. Therefore, there have been such drawbacks that a defective writing or destruction of data due to voltage drop occurs.